Filters are commonly used in electronic systems such as signal processing and data processing circuits to remove noise from a data signal. A digital finite impulse response (DFIR) filter applies a mathematical operation to a digital data stream to achieve any of a wide range of desired frequency responses. As illustrated in FIG. 1, a DFIR filter 100 passes an input 102 through a series of delay elements 104, 106 and 110, multiplying the delayed signals by filter coefficients or tap weights 112, 114, 116 and 120, and summing the results to yield a filtered output 122. The outputs 130, 140 and 150 of each delay element 104, 106 and 110 and the input 102 form a tapped delay line and are referred to as taps. The number of delay elements 104, 106 and 110, and thus the number of taps 102, 130, 140 and 150 (also referred to as the order or length of the DFIR filter 100) may be increased to more finely tune the frequency response, but at the cost of increasing complexity. The DFIR filter 100 implements a filtering equation such as Y[n]=F0X[n]+F1X[n−1]+F2X[n−2]+F3X[n−3] for the three-delay filter illustrated in FIG. 1, or more generally Y[n]=F0X[n]+F1X[n−1]+F2X[n−2]+ . . . +F3X[n−L], where X[n] is the current input 102, the value subtracted from n represents the index or delay applied to each term, Fi are the tap weights 112, 114, 116 and 120, Y[n] is the output 122 and L is the filter order. The input 102 is multiplied by tap weight 112 in a multiplier 124, yielding a first output term 126. The second tap 130 is multiplied by tap weight 114 in multiplier 132, yielding a second output term 134, which is combined with first output term 126 in an adder 136 to yield a first sum 148. The third tap 140 is multiplied by tap weight 116 in multiplier 142, yielding a third output term 144, which is combined with first sum 148 in adder 146 to yield a second sum 158. The fourth tap 150 is multiplied by tap weight 120 in multiplier 152, yielding a fourth output term 154, which is combined with second sum 158 in adder 156 to yield output 122. By changing the tap weights 112, 114, 116 and 120, the filtering applied to the input 102 by the DFIR filter 100 is adjusted to select the desired pass frequencies and stop frequencies.
In a data processing circuit, an analog to digital converter (ADC) is often used upstream of a DFIR filter to convert an analog signal to a digital signal that may be filtered in the DFIR filter and otherwise processed in other circuits. The sampling phase of the ADC may be selected or varied to meet any of a number of objectives in the data processing circuit, for example to minimize bit errors. However, DFIR filters may be sensitive to the selection of the ADC sampling phase, yielding various frequency responses to different ADC sampling phases. Adjusting the ADC sampling phase based on the frequency response of the DFIR filter may further complicate the meeting of other objectives of the data processing circuit related to the ADC sampling phase, as well as being time consuming.
Thus, for at least the aforementioned reason, there exists a need in the art for reducing DFIR filter sensitivity to ADC sampling phase.